During the developmental phase of new semiconductor technology, test wafers are designed to conduct electrical tests to characterize device performance and collect yield information associated with defective failure mechanisms. Each test wafer may include an array of die, and each die may include one or more integrated circuits that may be designated as test structures. To determine the yield and defect density associated with the test structures in the new technology, various tests may be performed on the test structures. During the tests, information may be read from, written to, or otherwise gathered from each test structure. The testing usually generates large amounts of data. The large amounts of data may include data for yield-related test structures and may include, for example, data relating to approximately 2000 parameters about each yield-related test structure. The test data is then manually analyzed to determine the yield, or percentage of properly functioning test structures in the lot of wafers. As a corollary, the test data is manually analyzed to determine the defects occurring the most frequently. Because the test data is analyzed manually, the analysis associated with the numerous parameters tested on a test wafer is time consuming, and in some instances may exceed a week. Accordingly, the analysis of test structures slows the development of new technologies and impedes the ability of the developmental staff to make new discoveries and improvements.